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| Micro Networks An Integrated Circuit Systems Company M2004-02 Preliminary Specifications M2004-02 Frequency Synthesizer DESCRIPTION The M2004-02 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz. The input to the Frequency Synthesizer is provided by selecting between a differential input clock or a single ended input clock. The output frequency is an integer multiple of the input reference frequency. The multiplying factor is programmed via a 6 bit parallel address. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The bandwidth control, low phase noise, and HOLD features make the M2004-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications. FEATURES Output Clock Frequency up to 700MHz Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Differential Input Compatible with LVPECL, LVDS, HSTL, SSTL, etc. Dual Input MUX Parallel Programming Tunable Loop Filter Response Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package APPLICATIONS SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator ISO 9001 Registered Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 1 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM M2004-02 Preliminary Specifications Functional Description: The internal PLL will adjust the VCSO output frequency to be M (feedback divider) times the selected input reference clock frequency. Note that the product of M x the input reference frequency The multiplying factor is programmed via a 6-bit parallel bus. The relationship between the VCSO frequency, the M divider, and the Differential Input reference clock is defined as follows: F VCSO = F REF_CLK x M OP_IN nOP_IN OP_OUT nOP_OUT Vc nVc When the N output divider is included, the complete relationship for the output frequency is defined as: F OUT nF OUT DIF_REF 0 nDIF_REF 0 Mux REF_CLK Phase Detector & Active Loop Filter VCSO Output Divider FOUT = F VCSO = F REF_CLK x M N N The N1 input can be hard wired to set the N divider to a specific state that will automatically occur during power-up. REF_SEL +M N1 M5:M0 Parallel Programming Interface MR must be such that it falls within the "lock" range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 2 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2 Rloop OP_IN Cloop M2004-02 Preliminary Specifications The M2004-02 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2. Rpost nVc Cpost nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency VCSO Frequency M N FOUT Rloop Cloop Rpost Cpost 19.44MHz 622.0800MHz 32 1 622.0800MHz 5k 1MF 20k 250pf Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 3 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PIN DESCRIPTIONS TABLE 2 Pin Number Name M2004-02 Preliminary Specifications 1, 2, 3 4, 9 5, 8 6, 7 10, 14, 26 11, 19, 33 12, 13 GND OP_IN, nOP_IN nOP_OUT, OP_OUT nVC, VC GND VCC N0, N1 I/O GND Configuration Description Power Supply Ground Analog I/O Analog I/O Input GND Power Input Pull - down Used for external loop filter. See Figure 2. Used for external loop filter. See Figure 2 VCSO Differential Control Voltage Input Pair Power Supply Ground Positive Supply Pins Determines the output divider value as defined in Table 3C. LVCMOS / LVTTL interface levels. 15, 16 17 FOUT, nFOUT MR Output Input Unterminated Pull - down Differential output, 3.3V LVPECL levels. Logic HIGH resets the reference frequency and N output dividers. Logic LOW enables the outputs. LVCMOS / LVTTL interface levels. 18, 20, 21 22 NC REF_SEL Input Pull - down No Connection Selects between the different reference clock inputs as the PLL reference source. See table 3D. LVCMOS / LVTTL interface levels. 23 24 25 27, 28, 29, 30, 31 32 34, 35, 36 NDIF_REF DIF_REF REF_ CLK Input Input Input Pull - down Pull - down Pull - down Pull - down Pull - down Inverting differential clock input. Compatible logic levels include LVCMOS, LVDS, HSTL, etc. Non-inverting differential clock input. Compatible logic levels include LVCMOS, LVDS, HSTL, etc. Input reference clock. LVCMOS / LVTTL interface levels. M divider inputs. Data is always transparent. No latch signal is required. M0, M1, M2, M3, M4 Input M5 DNC Input Do not connect. Internal test pins. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 4 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PIN CHARACTERISTICS TABLE 4 Symbol M2004-02 Preliminary Specifications CIN RPULLUP RPULLDOWN Parameter Input Capacitance Test Conditions Min Typical Max Units 4 51 51 pF k k Input Pullup Resistor Input Pulldown Resistor PARALLEL & SERIAL MODES FUNCTION TABLE 5A MR Inputs M N Conditions H L X Data X Data Reset, Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. Note: L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition PROGRAMMABLE VCSO FREQUENCY FUNCTION TABLE 5B VCSO Frequency (MHz) M Divide 325 350 375 400 * * 600 625 650 13 14 15 16 * * 24 25 26 32 M5 0 0 0 0 * * 0 0 0 16 M4 0 0 0 1 * * 1 1 1 8 M3 1 1 1 0 * * 1 1 1 4 M2 1 1 1 0 * * 0 0 0 2 M1 0 1 1 0 * * 0 0 1 1 M0 1 0 1 0 * * 0 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 5 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PARALLEL MODE FUNCTION TABLE 5C Inputs N Divider Output Frequency (MHz) N1 N0 Value Min Max TABLE 5D M2004-02 Preliminary Specifications SERIAL MODE FUNCTION Inputs REF SEL Reference 0 0 1 1 0 1 0 1 1 2 4 8 311 155.5 77.75 38.875 700 350 175 87.5 0 1 DIFF_REF REF_CLK POWER SUPPLY DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units VDD IDD Power Supply Voltage Power Supply Current 3.135 3.3 162 3.465 V mA VCC= 3.3V 5%, TA= 0C to 70C DIFFERENTIAL INPUT DC CHARACTERISTICS Symbol Parameter Test Conditions Min Max Units IIH IIL VP-P VCMR Input High Current Input Low Current nDIF_REF DIF_REF nDIF_REF DIF_REF -150 -5 0.15 5 150 A A A A V V Peak to Peak Input Voltage REF_SEL, REF_CLK VCC +0.3 VCC -0.85 VCC = 3.3V 5%, TA = 0C to 70C LVCMOS/LVTTL DC CHARACTERISTICS Symbol Parameter Test Conditions Min Max Units VIH VIL IIH Input High Voltage Input Low Voltage Input High Current REF_SEL, REF_CLK, N0:N1, M0:M5, MR REF_SEL, N0:N1, M0:M5, MR REF_CLK M5 N0, N1, MR, M0:M4, S_CLOCK, REF_SEL, REF_CLK M5 N0, N1, MR, M0:M4, REF_SEL, REF_CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V 2 VCC + 0.3 V -0.3 1.3 5 150 V A A A A IIL Input Low Current -150 -5 Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 6 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company LVPECL DC CHARACTERISTICS Symbol Parameter Signal Min Max M2004-02 Preliminary Specifications Units VOH VOL VSWING Output High Voltage: Note 1 Output Low Voltage: Note 1 Peak-to-Peak Output Voltage Swing FOUT, nFOUT FOUT, nFOUT FOUT, nFOUT VDD - 1.4 VDD - 2.0 0.6 Vcc - 1.0 Vcc - 1.7 0.85 V V V Note 1: Output terminated with 50 to VDD-2.V INPUT FREQUENCY CHARACTERISTICS Symbol Parameter Test Conditions Min Max Units FIN Input Frequency DIF_REF nDIF_REF 10 10 175 175 MHz MHz VCC = 3.3V5%, TA = 0C to 70C AC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units FOUT ONOISE Output Frequency Single Side Band Phase Noise 1kHz offset 10kHz offset 100kHz offset 12kHz to 20 MHz FOUT = 155MHz FOUT = 311MHz FOUT= 622MHz FOUT = 155MHz FOUT = 311MHz FOUT = 622MHz 20% to 80%, each output of pair measured is terminated into 50 load biased at Vcc-2V 20% to 80%, each output of pair measured is terminated into 50 load biased at Vcc-2V 38.88 -72 -94 -123 0.69 50 350 325 200 350 325 200 450 425 275 450 425 275 667 MHz dBc/Hz dBc/Hz dBc/Hz ps % J (t) odc tR (Note 1) Jitter (RMS) Output Duty Cycle Output Rise Time for output pairs FOUT0, nFOUT0 & FOUT1, nFOUT1 550 500 350 550 500 350 1 ps ps ps ps ps ps ms tF (Note 1) Output Fall Time for output pairs FOUT0, nFOUT0 & FOUT1, nFOUT1 tLOCK PLL Lock Time Note: The output frequencies of 155MHz, 311MHz and 622MHz were chosen for device characterization as these are common optical network clock frequencies. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 7 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PARAMETER MEASUREMENT INFORMATION M2004-02 Preliminary Specifications INPUT AND OUTPUT RISE AND FALL TIME 80% 80% V 20% Clock Inputs and Outputs t t 20% SWING R F ODC & tPERIOD Pulse Width t t odc = t PW PERIOD PERIOD Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 8 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company TEST EVALUATION BOARD M2004-02 Preliminary Specifications J3 9-PIN D CONNECTOR Pin Signal SW1 1 3 5 7 9 MR S_CLOCK S_DATA S_LOAD nP_LOAD Position Off On JP1: N0 JP2: N1 1 REF Select 2 M5 3 M4 4 M3 5 M2 6 M1 7 M0 8 N/C REF_CLK0 REF_CLK1 "1" "0" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" N/C N/C Logic "1" when installed Logic "0" when installed Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 9 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company MECHANICAL DIMENSIONS & PIN CONFIGURATION M2004-02 Preliminary Specifications .354 [9.0] #27 #28 #19 #18 .354 [ ] [9.0] #36 #10 .110 [2.8] ORIENTATION TAB Pin #1 .200 [5.1] .025 [0.6] C C L .041 [1.0] R.006 [R0.2] .007 [0.2] Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Designation GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN GND VCC NO N1 GND FOUT nFOUT MR Pin# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34, 35, 36 Designation N/C VCC N/C N/C REF_SEL nDIF_REF DIF_REF REF_CLK GND M0 M1 M2 M3 M4 M5 VCC DNC Dimensions are in inches, (dimensions) are in mm. ORDERING INFORMATION PART NUMBER Series Model VCSO Center Frequency (i.e. 622.0800MHz) M2004-02-622.0800 Available VCSO Frequencies 500.0000 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830 Micro Networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. Contact your nearest Micro Networks sales representative office for the latest specifications. Micro Networks An Integrated Circuit Systems Company 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.c2 Rev. 7.3 www.micronetworks.com |
Price & Availability of M2004-02-6691281
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